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500 MHz to 1700 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5358
FEATURES
RF frequency range of 500 MHz to 1700 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.3 dB SSB noise figure of 9.9 dB SSB noise figure with 5 dBm blocker of 23 dB Input IP3 of 25.2 dBm Input P1dB of 10.6 dBm Typical LO drive of 0 dBm Single-ended, 50 RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle, 6 mm x 6 mm, 36-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
MNGM COMM MNON MNOP MNLG MNLE VPOS VPOS NC
MNIN MNCT COMM VPOS COMM VPOS COMM DVCT DVIN
LOI2 VGS2 VGS1 VGS0 LOSW PWDN VPOS
APPLICATIONS
Cellular base station receivers Transmit observation receivers Radio link downconverters
ADL5358
COMM LOI1
COMM
GENERAL DESCRIPTION
The ADL5358 uses a highly linear, doubly balanced, passive mixer core along with integrated RF and local oscillator (LO) balancing circuitry to allow single-ended operation. The ADL5358 incorporates the RF baluns, allowing for optimal performance over a 500 MHz to 1700 MHz RF input frequency range. Performance is optimized for RF frequencies from 500 MHz to 1200 MHz using a high-side LO and RF frequencies from 1200 MHz to 1700 MHz using a low-side LO. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than -20 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.3 dB and can be used with a wide range of output impedances. The ADL5358 provides two switched LO paths that can be used in TDD applications where it is desirable to ping-pong between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5358 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<300 A) the circuit when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 1.
The ADL5358 is fabricated using a BiCMOS high performance IC process. The device is available in a 6 mm x 6 mm, 36-lead LFCSP and operates over a -40C to +85C temperature range. An evaluation board is also available. Table 1. Passive Mixers
RF Frequency (MHz) 500 to 1700 1200 to 2500 Single Mixer ADL5367 ADL5365 Single Mixer and IF Amp ADL5357 ADL5355 Dual Mixer and IF Amp ADL5358 ADL5356
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
07885-001
VPOS
DVOP
DVGM
VPOS
DVLE
DVON
DVLG
NC
ADL5358 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Performance ........................................................................... 4 3.3 V Performance ........................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 5 V Performance ........................................................................... 7 3.3 V Performance ...................................................................... 15 Spurious Performance ............................................................... 16 Circuit Description......................................................................... 17 RF Subsystem .............................................................................. 17 LO Subsystem ............................................................................. 18 Applications Information .............................................................. 19 Basic Connections ...................................................................... 19 IF Port .......................................................................................... 19 Bias Resistor Selection ............................................................... 19 Mixer VGS Control DAC .......................................................... 19 Evaluation Board ............................................................................ 21 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
11/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5358 SPECIFICATIONS
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, ZO = 50 , VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted. Table 2.
Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current Conditions Tunable to >20 dB over a limited bandwidth 500 Differential impedance, f = 200 MHz Externally generated 30 3.3 -6 230||0.75 5.0 0 13 50 450 5.5 +10 Min Typ 20 50 1700 Max Unit dB MHz ||pF MHz V dBm dB MHz V V V ns ns A A
530 1.0
1670
0.4 1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled 160 230 0 70
1 2
Apply supply voltage from external circuit through choke inductors. PWDN function is intended for use with VS 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5358
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 , unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious IF Channel-to-Channel Isolation POWER SUPPLY Positive Supply Voltage Quiescent Current Total Quiescent Current Conditions Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 200 differential 5 dBm blocker present 10 MHz from wanted RF input, LO source filtered fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at -10 dBm fRF1 = 900 MHz, fRF2 = 950 MHz, fLO = 1103 MHz, each RF tone at -10 dBm Unfiltered IF output Min 7.6 Typ 8.3 14.6 9.9 23 25.2 57 10.6 -33 -31 -43 -72 -79 54 4.75 LO supply IF supply 5 170 180 350 5.25 Max 8.6 Unit dB dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc dB V mA mA mA
22
-10 dBm input power -10 dBm input power
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.2 k, R2 = R5 = 400 , VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 , unless otherwise noted. Table 4.
Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) POWER INTERFACE Supply Voltage Quiescent Current Total Quiescent Current Conditions Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 , differential ZLOAD = 200 differential fRF1 = 899.5 MHz, fRF2 = 900.5 MHz, fLO = 1103 MHz, each RF tone at -10 dBm fRF1 = 950 MHz, fRF2 = 900 MHz, fLO = 1103 MHz, each RF tone at -10 dBm Min Typ 8.3 14.6 8.9 19.3 47.2 6.75 3.0 Resistor programmable Device disabled 3.3 200 300 3.6 Max Unit dB dB dB dBm dBm dBm V mA A
Rev. 0 | Page 4 of 24
ADL5358 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage, VS RF Input Level LO Input Level MNOP, MNON, DVOP, DVON Bias VGS2, VGS1, VGS0, LOSW, PWDN Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 2.2 W 22C/W 150C -40C to +85C -65C to +150C 260C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 5 of 24
ADL5358 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPOS MNGM COMM MNON MNOP MNLE VPOS MNLG NC
36 35 34 33 32 31 30 29 28
MNIN MNCT COMM VPOS COMM VPOS COMM DVCT DVIN
1 2 3 4 5 6 7 8 9
ADL5358
TOP VIEW (Not to Scale)
27 26 25 24 23 22 21
LOI2 VGS2 VGS1 VGS0 LOSW PWDN VPOS
20 COMM 19 LOI1
DVGM COMM DVOP DVON DVLE VPOS DVLG NC
VPOS 10 11 12 13 14 15 16 17 18
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3, 5, 7, 12, 20, 34 4, 6, 10, 16, 21, 30, 36 8 9 11 13, 14 15 17 18, 28 19 22 23 24, 25, 26 27 29 31 32, 33 35 Paddle Mnemonic MNIN MNCT COMM VPOS DVCT DVIN DVGM DVOP, DVON DVLE DVLG NC LOI1 PWDN LOSW VGS0, VGS1, VGS2 LOI2 MNLG MNLE MNOP, MNON MNGM EPAD Description RF Input for Main Channel. Internally matched to 50 . This pin must be ac-coupled. Center Tap for Main Channel Input Balun. Bypass this pin to ground using low inductance capacitor. Device Common (DC Ground). Positive Supply Voltage. Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor. RF Input for Diversity Channel. Internally matched to 50 . This pin must be ac-coupled. Diverstiy Amplifier Bias Setting. Connect a 1.3 k resistor to ground for typical operation. Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using external inductors. Diversity Channel IF Return. This pin must be grounded. Diverstiy Channel LO Buffer Bias Setting. Connect a 1 k resistor to ground for typical operation. No Connect. Local Oscillator Input 1. Internally matched to 50 . This pin must be ac-coupled. Connect to Ground for Normal Operation. Connect this pin to 3 V for disable mode when using VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V. Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2. Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level. Local Oscillator Input 2. Internally matched to 50 . This pin must be ac-coupled. Main Channel LO Buffer Bias Setting. Connect a 1 k resistor to ground for typical operation. Main Channel IF Return. This pin must be grounded. Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using external inductors. Main Amplifier Bias Setting. Connect a 1.3 k resistor to ground for typical operation. Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 24
07885-002
ADL5358 TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
400
70
380
SUPPLY CURRENT (mA)
65
TA = -40C
TA = -40C 360
INPUT IP2 (dBm)
60
TA = +25C TA = +85C
55 TA = +25C 50 TA = +85C
340
320
45
07885-003
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
12
Figure 6. Input IP2 vs. RF Frequency
14
11
13
CONVERSION GAIN (dB)
INPUT P1dB (dBm)
10 TA = -40C 9 TA = +25C 8
12 TA = +85C 11
TA = +25C
10
7 TA = +85C 6
TA = -40C
9
07885-004
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 4. Power Conversion Gain vs. RF Frequency
31
Figure 7. Input P1dB vs. RF Frequency
14 13
29
SSB NOISE FIGURE (dB)
12 11 10 9 8 7 6 700 TA = -40C TA = +25C
TA = +85C
INPUT IP3 (dBm)
27
TA = -40C
TA = +25C
25
23
TA = +85C
21
750
800
850
900
950
1000 1050 1100 1150 1200
07885-005
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
Figure 8. SSB Noise Figure vs. RF Frequency
Rev. 0 | Page 7 of 24
07885-008
19 700
07885-007
5 700
8 700
07885-006
300 700
40 700
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
400 VPOS = 5.25V 380
62 61 60 59
SUPPLY CURRENT (mA)
360
VPOS = 5.0V
INPUT IP2 (dBm)
58 57 56 55
VPOS = 5.0V
VPOS = 5.25V
340
VPOS = 4.75V
320
54 53
07885-009
VPOS = 4.75V
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. Supply Current vs. Temperature
10.0 4.75V 5.0V 5.25V
Figure 12. Input IP2 vs. Temperature
13
9.5
CONVERSION GAIN (dB)
12
INPUT P1dB (dBm)
VPOS = 5.25V
9.0
VPOS = 5.0V
11
8.5
10 VPOS = 4.75V 9
8.0
7.5
07885-010
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 10. Power Conversion Gain vs. Temperature
29 28 27
INPUT IP3 (dBm)
Figure 13. Input P1dB vs. Temperature
12.0 11.5
SSB NOISE FIGURE (dB)
VPOS = 5.25V
11.0 10.5 10.0 9.5 9.0 8.5 8.0 -40 -30 -20 -10 VPOS = 5.0V VPOS = 5.25V
26 25 VPOS = 5.0V 24 VPOS = 4.75V 23 22 21 -40 -30 -20 -10
VPOS = 4.75V
07885-011
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Input IP3 vs. Temperature
Figure 14. SSB Noise Figure vs. Temperature
Rev. 0 | Page 8 of 24
07885-014
07885-013
7.0 -40 -30 -20 -10
8 -40 -30 -20 -10
07885-012
300 -40 -30 -20 -10
52 -40 -30 -20 -10
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
400
70
65
380
SUPPLY CURRENT (mA)
TA = -40C
INPUT IP2 (dBm)
60 TA = +25C TA = -40C 55 TA = +85C 50
360
TA = +25C
340
TA = +85C 320
45
07885-015
30
80
130
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 15. Supply Current vs. IF Frequency
11 TA = -40C
Figure 18. Input IP2 vs. IF Frequency
13
10
12
TA = +85C
CONVERSION GAIN (dB)
9
INPUT P1dB (dBm)
11
8 TA = +25C 7 TA = +85C 6
10 TA = +25C 9 TA = -40C
5 4 30 80 130 180 230 280 330 380 430 IF FREQUENCY (MHz)
8
07885-016
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
Figure 16. Power Conversion Gain vs. IF Frequency
30 29 28 27 TA = -40C TA = +25C
Figure 19. Input P1dB vs. IF Frequency
14 13 12 11 10 9 8 7
07885-017
26 25 24 23 22 21 20 30 80 130
TA = +85C
SSB NOISE FIGURE (dB)
INPUT IP3 (dBm)
180
230
280
330
380
430
30
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Input IP3 vs. IF Frequency
Figure 20. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 9 of 24
07885-020
6
07885-019
7
07885-018
300
40
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
11.0 10.5 10.0
12.0
11.5
TA = -40C
TA = +85C
CONVERSION GAIN (dB)
INPUT P1dB (dBm)
9.5 9.0 8.5 8.0 7.5 7.0 6.5
07885-021
11.0
10.5 TA = +25C 10.0 TA = -40C 9.5
TA = +25C
TA = +85C
-6
-4
-2
0
2
4
6
8
10
-6
-4
-2
0
2
4
6
8
10
LO POWER (dBm)
LO POWER (dBm)
Figure 21. Power Conversion Gain vs. LO Power
30 29
-65 -60
Figure 24. Input P1dB vs. LO Power
28
IF/2 SPURIOUS (dBc)
27 INPUT IP3 (dBm) TA = -40C 26 25 24 23 22 21
07885-022
-70
-75
TA = +25C
TA = +25C
TA = +85C
-80 TA = +85C -85 TA = -40C
-6
-4
-2
0
2
4
6
8
10
750
800
850
900
950
1000 1050 1100 1150 1200
LO POWER (dBm)
RF FREQUENCY (MHz)
Figure 22. Input IP3 vs. LO Power
64 -65 -67 62 TA = -40C 60 -69
IF/3 SPURIOUS (dBc)
Figure 25. IF/2 Spurious vs. RF Frequency
-71 -73 -75 -77 -79 -81 TA = -40C
INPUT IP2 (dBm)
TA = +25C 58
TA = +25C
56 TA = +85C 54
TA = +85C
52 50 -6 -4 -2 0 2 4 6 8 10 LO POWER (dBm)
-83
07885-026
07885-023
-85 700
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 23. Input IP2 vs. LO Power
Figure 26. IF/3 Spurious vs. RF Frequency
Rev. 0 | Page 10 of 24
07885-025
20
-90 700
07885-024
6.0
9.0
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, ZO = 50 , VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
100 MEAN = 8.47 STANDARD DEVIATION = 0.66% 80 PERCENTAGE (%)
500
12
400
9
CAPACITANCE (pF)
07885-032
RESISTANCE ()
60
300
6
40
200
3
20
100
0
07885-027
7.5
8.0
8.5
9.0
9.5
10.0
80
130
180
230
280
330
380
430
CONVERSION GAIN (dB)
IF FREQUENCY (MHz)
Figure 27. Conversion Gain Distribution
100
MEAN = 25.2 STANDARD DEVIATION = 0.71 80
Figure 30. IF Output Impedance (R Parallel, C Equivalent)
10 12 14 RF RETURN LOSS (dB) 16 18 20 22 24 26 28
07885-028
PERCENTAGE (%)
60
40
20
15
18
21
24
27
30
33
750
800
850
900
950
1000 1050 1100 1150 1200
INPUT IP3 LO (dBm)
RF FREQUENCY (MHz)
Figure 28. Input IP3 Distribution
100 MEAN = 10.66 STANDARD DEVIATION = 0.96 80 LO RETURN LOSS (dB) PERCENTAGE (%)
Figure 31. RF Return Loss, Fixed IF
8 9 10 SELECTED 11 12 13 14 15 16
07885-029
60
40
UNSELECTED
20
0 7 8 9 10 11 12 13 INPUT P1dB (dBm)
17 900
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (GHz)
Figure 29. Input P1dB Distribution
Figure 32. LO Return Loss, Selected and Unselected
Rev. 0 | Page 11 of 24
07885-031
0
30 700
07885-030
0 7.0
0 30
-3
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, ZO = 50 , VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
65
-24 -26
LO-TO-RF LEAKAGE (dBm)
LO SWITCH ISOLATION (dB)
60
TA = +25C TA = +85C
-28 -30 -32 -34 -36 -38 900
TA = -40C
55
TA = -40C
50
TA = +25C TA = +85C
45
07885-033
750
800
850
900
950
1000 1050 1100 1150 1200
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 33. LO Switch Isolation vs. RF Frequency
-20 -25 -5 0
Figure 36. LO-to-RF Leakage vs. LO Frequency
RF-TO-IF ISOLATION (dB)
-30 TA = +85C -35 -40 -45 TA = -40C -50 -55 2XLO-TO-IF
07885-034
2XLO LEAKAGE (dBm)
-10
TA = +25C
-15 2XLO-TO-RF -20
-25
750
800
850
900
950
1000 1050 1100 1150 1200
950
RF FREQUENCY (MHz)
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
Figure 34. RF-to-IF Isolation vs. RF Frequency
-20
0 -10
Figure 37. 2XLO Leakage vs. LO Frequency
-25
LO-TO-IF LEAKAGE (dBm)
TA = -40C -30
3XLO LEAKAGE (dBm)
-20 -30 3XLO-TO-RF -40 -50 -60 3XLO-TO-IF -70 900
-35 TA = +25C TA = +85C -45
-40
07885-035
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
950
1000 1050 1100 1150 1200 1250 1300 1350 1400 LO FREQUENCY (MHz)
Figure 35. LO-to-IF Leakage vs. LO Frequency
Figure 38. 3XLO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
07885-038
-50 900
07885-037
-60 700
-30 900
07885-036
40 700
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
9 14
30
8
13
25
SSB NOISE FIGURE (dB)
CONVERSION GAIN (dB)
SSB NOISE FIGURE (dB)
7
12
20
6
11
15
5
10
10
4
750
800
850
900
950
07885-039
-25
-20
-15
-10
-5
0
5
10
RF FREQUENCY (MHz)
BLOCKER POWER (dBm)
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for Various VGS Settings
13 12 11 INPUT P1dB (dB) 10 9 8 7 6 700 VGS = 000 VGS = 011 VGS = 100 VGS = 110 750 800 850 900 950 45 40
Figure 42. SSB Noise Figure vs. 10 MHz Offset Blocker Level
300 280 260
35 INPUT IP3 (dB) 30 25 20 15 10 1000 1050 1100 1150 1200
SUPPLY CURRENT (mA)
IF RESISTOR SUPPLY CURRENT 240 220 200 180 160 LO RESISTOR SUPPLY CURRENT 140 120
07885-040
700
800
900
1000 1100 1200 1300 1400 1500 1600
RF FREQUENCY (MHz)
BIAS RESISTOR VALUE ()
Figure 40. Input P1dB and Input IP3 vs. RF Frequency for Various VGS Settings
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value
28 INPUT IP3 16 14 12 NOISE FIGURE 10 8 CONVERSION GAIN 6 4 600 4 12 24 20
INPUT IP3 (dBm)
07885-044
16 14 INPUT IP3 12 NOISE FIGURE 10 8 CONVERSION GAIN 6 4 2 600
32 28 24 20 16 12 8 4 1000 1100 1200 1300 1400 1500 1600
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
18
INPUT IP3 (dBm)
16
8
700
800
900
07885-041
700
800
900
0 1000 1100 1200 1300 1400 1500 1600
LO BIAS RESISTOR VALUE ()
IF BIAS RESISTOR VALUE ()
Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias Resistor Value
Figure 44. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value
Rev. 0 | Page 13 of 24
07885-043
100 600
07885-042
3 700
VGS = 000 VGS = 011 VGS = 100 VGS = 110
9
5
8 1000 1050 1100 1150 1200
0 -30
ADL5358
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
60
IF CHANNEL-TO-CHANNEL ISOLATION (dB)
TA = -40C 59 58 57 56 55 54 53 700 TA = +85C TA = +25C
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 45. IF Channel-to-Channel Isolation vs. RF Frequency
Rev. 0 | Page 14 of 24
07885-045
ADL5358
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.2 k, R2 = R5 = 400 , VGS0 = VGS1 = VGS2 = 0 V, ZO = 50 , unless otherwise noted.
220
60
215 TA = -40C
SUPPLY CURRENT (mA)
INPUT IP2 (dBm)
55 TA = -40C 50 TA = +25C
210
205 TA = +25C
45 TA = +85C 40
200
195
TA = +85C
35
07885-046
750
800
850
900
950
1000 1050 1100 1150 1200
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
Figure 46. Supply Current vs. RF Frequency at 3.3 V
11
Figure 49. Input IP2 vs. RF Frequency at 3.3 V
10
10
CONVERSION GAIN (dB)
9 TA = -40C
INPUT P1dB (dBm)
9
8 TA = +25C 7
TA = +85C
8
TA = +25C
7
TA = +85C
6
TA = -40C
6
5
RF FREQUENCY (MHz)
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 47. Power Conversion Gain vs. RF Frequency at 3.3 V
26 24 22
INPUT IP3 (dBm)
Figure 50. Input P1dB vs. RF Frequency at 3.3 V
14 13 12
SSB NOISE FIGURE (dB)
TA = -40C
11 TA = +25C 10 9 8 7 6 5
TA = +85C
20 18 TA = +85C 16 14 12 700
TA = +25C
TA = -40C
RF FREQUENCY (MHz)
750
800
850
900
950
1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 48. Input IP3 vs. RF Frequency at 3.3 V
Figure 51. SSB Noise Figure vs. RF Frequency at 3.3 V
Rev. 0 | Page 15 of 24
07885-051
750
800
850
900
950
1000 1050 1100 1150 1200
07885-048
4 700
07885-050
750
800
850
900
950
1000 1050 1100 1150 1200
07885-047
5 700
4 700
07885-049
190 700
30 700
ADL5358
SPURIOUS PERFORMANCE
All spur tables are (N x fRF) - (M x fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = -100 dBm.
5 V Performance
VS = 5 V, IS = 350 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k, VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 , unless otherwise noted.
M 0 0 1 2 3 4 5 6 N7 8 9 10 11 12 13 14 -52.4 -74.8 <-100 <-100 <-100 <-100 1 -28.0 0.0 -73.1 <-100 <-100 <-100 <-100 <-100 2 -21.5 -70.8 -78.2 <-100 <-100 <-100 <-100 <-100 <-100 <-100 3 -59.0 -42.4 -90.2 -91.1 <-100 <-100 <-100 <-100 <-100 <-100 <-100 4 -44.2 -67.8 -77.6 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -71.2 -65.5 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -86.2 -91.0 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 7 8 9 10 11 12 13 14
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100
3.3 V Performance
VS = 3.3 V, IS = 200 mA, TA = 25C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, RF power = -10 dBm, R1 = R4 = 1.2 k, R2 = R5 = 400 , VGS0 = VGS1 = VG2 = 0 V, and ZO = 50 , unless otherwise noted.
M 0 0 1 2 3 4 5 6 N7 8 9 10 11 12 13 14 1 -33.3 -46.3 0.0 -68.2 -61.5 -99.9 -90.6 <-100 <-100 <-100 <-100 <-100 <-100 <-100 2 -23.7 -64.4 -78.4 -95.2 <-100 <-100 <-100 <-100 <-100 <-100 3 -49.1 -39.4 -81.2 -75.7 <-100 <-100 <-100 <-100 <-100 <-100 <-100 4 -41.3 -71.2 -71.8 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 5 -82.9 -73.1 -94.6 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 6 -86.1 -88.8 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 7 8 9 10 11 12 13 14
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100 <-100
<-100 <-100 <-100 <-100
Rev. 0 | Page 16 of 24
ADL5358 CIRCUIT DESCRIPTION
The ADL5358 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size. The RF subsystem consists of integrated, low loss RF baluns, passive MOSFET mixers, sum termination networks, and IF amplifiers. The LO subsystem consists of an SPDT-terminated FET switch and two multistage limiting LO amplifiers. The purpose of the LO subsystem is to provide a large, fixed amplitude balanced signal to drive the mixer independent of the level of the LO input. A simplified schematic of the device is shown in Figure 52.
MNGM COMM MNON MNOP MNLG MNLE VPOS VPOS NC
The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. Because the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M x N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and in the feedback elements in the IF amplifier. The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 . If operation in a 50 system is desired, the output can be transformed to 50 by using a 4:1 transformer. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure 41, Figure 43, and Figure 44 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. No performance enhancement is obtained by reducing the value of these resistors, and excessive dc power dissipation may result.
MNIN MNCT COMM VPOS COMM VPOS COMM DVCT DVIN
LOI2 VGS2 VGS1 VGS0 LOSW PWDN VPOS
ADL5358
COMM LOI1
COMM
Figure 52. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 500 MHz to 1700 MHz.
Rev. 0 | Page 17 of 24
07885-001
VPOS
DVOP
DVGM
VPOS
DVLE
DVON
DVLG
NC
ADL5358
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1100 MHz. The best operation is achieved with either high-side LO injection for RF signals in the 500 MHz to 1200 MHz range or low-side injection for RF signals in the 1200 MHz to 1700 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 500 MHz to 1700 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5358 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from -6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power. The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5358 has a power-down mode that permits the dc current to drop to <300 A. The logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn.
Rev. 0 | Page 18 of 24
ADL5358 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5358 mixer is designed to downconvert radio frequencies (RF) primarily between 500 MHz and 1700 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 53 depicts the basic connections of the mixer. It is recommended to ac-couple the RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN matching network consists of a series 8 pF capacitor to provide the optimized RF input return loss for the desired frequency band.
BIAS RESISTOR SELECTION
The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5) are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure 41, Figure 43, and Figure 44 provide the reference for the bias resistor selection when lower power consumption is preferred at the expense of conversion gain and IP3 performance.
MIXER VGS CONTROL DAC
The ADL5358 features three logic control pins, VGS0 (Pin 24), VGS1 (Pin 25), and VGS2 (Pin 26), that allow programmability for internal gate-to-source voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults VGS0, VGS1, and VGS2 to ground. Power conversion gain, NF, IIP3, and input P1dB can be optimized, as shown in Figure 39 and Figure 40.
IF PORT
The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss. The real part of the output impedance is approximately 200 , as seen in Figure 30, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Table 3. When a 50 output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 53.
Rev. 0 | Page 19 of 24
ADL5358
R10 MAIN_OUTN C33 T1 C19 C27 C17 C32 MAIN_OUTP
C8 L1 R3 VCC
C21 L2
C22 VCC
36 35
R1
C25
C18 VCC R2
28
34
33
32
31
30
29
C9 MAIN_IN Z1 Z2
1 27
C16 LO2 R12
2 26
R16 VCC
C3
C2
3 25
R7 R13 R8 R14
4 24
C34
R17
R11 R15
5 23
VCC
6
22
R19
7 21
VCC C26 C15
C6
C7
8
ADL5358
20
C11 DIV_IN Z3 Z4
10 11 12 13 14 15 16 17 18 9 19
LO1 C14
VCC VCC + GND L5 R6 L4 C10 C23 R4 VCC VCC C24 C13 R5
C1
C12
C28 C20 T2 DIV_OUTP C30 R9 C31 DIV_OUTN
07885-153
C29
Figure 53. Typical Application Circuit
Rev. 0 | Page 20 of 24
ADL5358 EVALUATION BOARD
An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 54. The evaluation board is fabricated using Rogers(R) RO3003 material.
R10 MAIN_OUTN C33 T1 C19 C27 C17 C32 MAIN_OUTP
Table 7 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 55 and Figure 56.
C8 L1
C21 L2 C25 C18 VCC R2
R3 VCC
C22 VCC
R1
VPOS
MNGM
COMM
MNOP
MNLE
VPOS
MNON
MNLG
C9 MAIN_IN Z1 Z2 C3 C2 COMM VPOS VGS1 VGS0 R13 R8 MNIN MNCT LOI2
NC
C16 LO2 R12 VGS2 R7 C34 R16 VCC
ADL5358
COMM VCC VPOS COMM C6 C11 DIV_IN Z3 Z4
DVGM COMM DVON DVOP VPOS VPOS DVLE DVLG
R14 LOSW R11 PWDN VPOS COMM R15
R17
TOP VIEW (Not to Scale)
C7 DVCT DVIN VCC LOI1 C26 C15 R19
LO1
NC
C14
VCC + GND L5 VCC C10 C23 R4 VCC C24 R6 L4 C13 VCC R5
C1
C12
C28 C20 T2 DIV_OUTP C30 R9 C31 DIV_OUTN
07885-154
C29
Figure 54. Evaluation Board Schematic
Rev. 0 | Page 21 of 24
ADL5358
Table 7. Evaluation Board Configuration
Components C1, C8, C10, C12, C13, C15, C18, C21, C22, C23, C24, C25, C26 Z1 to Z4, C2, C3, C6, C7, C9, C11 Description Power Supply Decoupling. Nominal supply decoupling consists of a 0.01 F capacitor to ground in parallel with 10 pF capacitors to ground positioned as close to the device as possible. RF Main and Diversity Input Interface. Main and diversity input channels are ac-coupled through C9 and C11. Z1 to Z4 provide additional component placement for external matching/filter networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional supply bypassing. T1 and T2 are 4:1 impedance transformers used to provide a single-ended IF output interface with C27 and C28 providing center-tap bypassing. C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled output interface. Remove R9 and R10 for balanced output operation. LO Interface. C14 and C16 provide ac coupling for the LOI1 and LOI2 local oscillator inputs. LOSW selects the appropriate LO input for both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled when the LOSW jumper is removed. Jumper can be removed to allow LOSW interface to be exercised using an external logic generator. PWDN Interface. When the PWDN 2-pin shunt is inserted, the ADL5358 is powered down. When R19 is open, it pulls the PWDN logic low and enables the device. Jumper can be removed to allow PWDN interface to be exercised using an external logic generator. Grounding the PWDN pin is allowed during nominal operation but is not permitted when supply voltages exceed 3.3 V. Bias Control. R16 and R17 form a voltage divider to provide a 3 V for logic control, bypassed to ground through C34. R7, R8, R11, R12, R13, and R14 provide resistor programmability of VGS0, VGS1, and VGS2. Typically, these nodes can be hardwired for nominal operation. Grounding these pins is allowed for nominal operation. R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set the bias point for the internal IF amplifiers. Default Conditions C1, C8, C12, C21 = 150 pF (Size 0402), C10 = 4.7 F (Size 3216), C13, C15, C18 = 0.1 F (Size 0402) C22, C23, C24, C25, C26 = 10 pF (Size 0402) Z1, Z3 = open (Size 0402), Z2, Z4 = open (Size 0402), C2, C7 = 10 pF (Size 0402), C3, C6 = 0.01 F (Size 0402), C9, C11 = 8 pF (Size 0402) T1, T2 = TC4-1T+ (Mini-Circuits), C17, C19, C20, C29 to C33 = 0.001 F (Size 0402), C27, C28 = 150 pF (Size 0402), L1, L2, L4, L5 = 330 nH (Size 0805), R3, R6, R9, R10 = 0 (Size 0402)
T1, T2, C17, C19, C20, C27 to C33, L1, L2, L4, L5, R3, R6, R9, R10
C14, C16, R15, LOSW
C14, C16 = 10 pF (Size 0402), R15 = 10 k (Size 0402), LOSW = 2-pin shunt
R19, PWDN
R19 = 10 k (Size 0402), PWDN = 2-pin shunt
R1, R2, R4, R5, R7, R8, R11 to R14, R16, R17, C34
R1, R4 = 1.3 k (Size 0402), R2, R5 = 1 k (Size 0402), R7, R8, R11 = 0 (Size 0402), R12, R13, R14 = open (Size 0402), R16 = 10 k (Size 0402), R17 = 15 k (Size 0402), C34 = 1 nF (Size 0402)
07885-056
Figure 55. Evaluation Board Top Layer
Figure 56. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
07885-057
ADL5358 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
28 27 36
PIN 1 INDICATOR
1
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC
EXPOSED PAD 0.75 0.60 0.50
(BOTTOM VIEW)
3.85 3.70 SQ 3.55
9
19 18
10
0.20 MIN 4.00 REF
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1
Figure 57. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6mm x 6 mm Body, Very Thin Quad (CP-36-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5358ACPZ-R2 1 ADL5358ACPZ-R71 ADL5358-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 36-Lead LFCSP_VQ 36-Lead LFCSP_VQ Evaluation Board
Package Option CP-36-1 CP-36-1
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
050808-D
0.35 0.28 0.23
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
ADL5358 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07885-0-11/09(0)
Rev. 0 | Page 24 of 24

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